Website Silicon Therapeutics


Silicon Therapeutics is an integrated computational drug discovery company focused on developing novel medicines for diseases with targets that are currently considered to be challenging for traditional approaches. Our INSITE platform closely represents the real dynamical nature of targets using accurate all-atom simulations, enabling us to design and optimize compounds for targets that were previously considered “undruggable.” We foster a collaborative, respectful, and flexible work environment that allows individuals to thrive. Our supportive and open work environment enhances synergies among individuals, thereby maximizing the quality and efficiency of our efforts. We embrace diversity and value different perspectives, ideas, and identities of everyone on the team.

High-performance computing (HPC) is central to operations at Silicon Therapeutics —we currently have hundreds of GPUs and thousands of CPUs constantly at work solving problems for our drug discovery efforts. Our next-generation architecture efforts are focused on FPGAs to solve problems in drug discovery that cannot scale across many CPUs, GPUs, and other commodity architectures.  We are currently looking for an FPGA developer to work on this effort. The ideal candidate will have a background in FPGA development in VHDL but also high-level languages such as HLS and OpenCL on both Intel and Xilinx FPGAs.


  • Implement logic design for algorithms currently implemented in OpenCL
  • Work on optimal layout and placement for molecular dynamic, quantum chemistry, and other algorithms in drug discovery
  • Work with Intel and Xilinx’s network IP technologies such as SerialLite and Aurora to connect FPGA transceivers directly for communication
  • Diagnose bottlenecks and limitations of designs generated using languages such as OpenCL and replace those designs with optimized implementations in VHDL or Verilog


  • PhD with 3+ years of HPC experience
  • Expertise with logic design on Intel and Xilinx FPGAs using VHDL, Verilog, OpenCL, HLS.
  • Skilled with Quartus and Vivado suites
  • Background in programming transceivers using network IP from Intel and Xilinx such as SerialLite and Aurora.
  • Experience combining VHDL with network IP and HLS is highly desirable
  • Experience with mixed language programming skills for FPGAs are highly desired
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